Model Verification and Validation : Closed Loop Testing

Closed Loop Testing

For model verification and validation it is not sufficient to analyze the System Under Test (SUT) in an open-loop mode alone. As most systems interact with their environment closed-loop they also have to be tested closed-loop. Two approaches are suggested for closed loop testing:

One is, to use testbench charts. As long as the behavior of data sources and sinks identified in the context diagram (refer to Capturing the System Context (“Extended System Context”) and Building the Conceptual Model) can be described by state-machines, the loop can be closed through respective testbench charts applying the mechanism of Broadcasting.

Note: For the validation of the interfaces within the system, the testbench charts should only generate operational inputs.

Another approach would be to close the loop at the extended context diagram level. Refer to Capturing the System Context (“Extended System Context”). Each of the identified nodes should be modeled with respect to its interaction with the SUT:

If time-continuous (e.g. capturing sensor / actuator dynamics) using the VisSim tool within Rational Statemate. In this case, a testbench chart should only be used to monitor and/or induce system disturbances (e.g. in an FMEA analysis).

As the extended context diagram corresponds to the later system integration layer, this approach additionally validates the operational interfaces between the SUD and its respective data sources and sinks.