Methodology : The Rational Statemate Approach : System Validation

System Validation

A characteristic of the V-Process model is that as the engineers progress down the left leg of the V, tests must be defined at each stage to be used in the later system integration.

What this means in terms of our analysis process is that at every level of the system hierarchy, before proceeding to the next level, the model should be validated by simulation. During this simulation, the stimulus and response can then be recorded. This provides the test definition in terms of applied input and expected output to be used at integration. As part of the analysis, the code generator should be used to produce a C prototype that serves as a functional executable.

Graphical panels should be used to drive/control the simulation. The panel could be a mock up of the real user interface, but panels are also very useful for condensing information and can be used as a system monitor exhibiting values, system objects, modes, etc. Panels also serve as an excellent communications medium from designers to managers, marketing, and customers since they can show the system operation at any level of abstraction. For these reasons, time spent creating clear understandable panels is time well spent.

As all systems are part of a control loop, system validation must be performed closed-loop to ensure accuracy. Closed-loop analysis requires modeling the external environment such that if a change of output affects an input then this is modeled and simulated.

In the early stages of analysis, up to System Level 2, Rational Statemate linear testbench models are sufficiently accurate to model the external environment and close the loop (see the Closed-Loop Validation by Linear Testbench-Models figure). The testbench is used to model the essential behavior of the external activities. Testbenches can use concurrency, broadcasting, and global visibility for effective testing of the system under development.

As the model becomes more detailed, generally more accurate non-linear models of the environment are required to accurately verify the system. C Code models, either hand written or generated from other SE tools, are used to model the external environment (refer to Rational Statemate in a Systems-Engineering Environment)

To do this, include the C code as a basic activity in a higher level Activity-chart with the system model in the other activity as shown in the Closed-Loop Validation by a Non-linear Plant-Model (User C-Code) figure.

Note: In the Closed-Loop Validation by a Non-linear Plant-Model (User C-Code) figure, a Non-Linear Plant Model replaces the sensors and actuators in the Closed-Loop Validation by Linear Testbench-Models figure.

Using this Bottom-up expansion, and linking C code to a basic activity allows interactive simulation with the closed-loop C code and provides an easy transition to prototyping with generated code.

When creating these models of the external environment, be careful not to fall into the trap of spending vast resources on creating these models and forever refining them to be more detailed. The aim is to build confidence in the system model to the point where the engineers are confidant that in switching to HW-in-the-loop analysis there will not be a catastrophic system failure. Once this confidence has been established the switch should be made to HW-in-the-loop validation.

Using the generic approach of the bus interface (refer to Functional Decomposition - System Levels > 2), the system model can be validated at an advanced state of system definition by connecting into the network and evaluating the algorithm in its intended environment. The product can be operated with this prototype and final optimizations and testing can be performed. This HW-in-the-loop analysis is really the ultimate in verification and provides absolute confidence that the specification is correct and the system will work when built.

Because the Rational Statemate testbench is not part of the system specification, concurrency and broadcast can be freely used. In fact, the broadcast mechanism gives testbenches the capability to see down into the model and monitor or change any variable. This is a very powerful capability and means testbenches can be used for a variety of different applications such as:

 

 

Closed-Loop Validation by Linear Testbench-Models
Closed-Loop Validation by a Non-linear Plant-Model (User C-Code)